Circuit designers perform timing analysis to determine whether not a design will satisfy timing requirements when implemented. Timing analysis may be either static or dynamic. Static timing analysis may entail computing the delays of signal paths in the circuit design based on the routes defined for the signals. Dynamic timing analysis may involve a simulation using the circuit design for determining the delays of the signal paths.
In one approach to static timing analysis, a placed and routed circuit design is analyzed using a standard delay library. The standard delay library has elements that correspond to particular circuit resources of an integrated circuit (IC) on which the circuit design is to be implemented. The elements in the standard library have associated delay values, and the delays of paths in the placed and routed circuit design are computed based on the components in the circuit design and matching elements and associated delay values from the standard delay library.
Static timing analysis may produce delay values that are too conservative, which may cause difficulties in closing the timing of a circuit design. Different instances of a component of an IC may have different delays depending on the location of the component on the IC, the type of another component that drives the component, and the type of the component that the component is driving, for example. The delay values in a standard delay library may reflect a worst case delay for the component of the IC that is represented by the associated element.